From dc0a3308cbf55c99d8aff8948d658fd2bd3d4cb5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krystian=20Bac=C5=82awski?= Date: Sun, 19 May 2013 15:49:00 +0200 Subject: [PATCH] Preparation for gcc 3.4.6 import. --- bootstrap.conf | 2 +- bootstrap.sh | 9 +- .../NDK_3.9/Include/include_h/inline/macros.h | 478 ++++++++++++------ 3 files changed, 340 insertions(+), 149 deletions(-) diff --git a/bootstrap.conf b/bootstrap.conf index ef024c2..a658a4a 100644 --- a/bootstrap.conf +++ b/bootstrap.conf @@ -36,7 +36,7 @@ readonly LIBM_SRC="${LIBM}.tar.gz" readonly LIBNIX="libnix-2.1" readonly LIBNIX_SRC="${LIBNIX}.tar.gz" -# Needed by GCC 2.95.3 +# Needed by GCC 2.95.3 and 3.4.6 readonly BISON="bison-1.35" readonly BISON_SRC="${BISON}.tar.gz" diff --git a/bootstrap.sh b/bootstrap.sh index 1f2be8e..57574af 100755 --- a/bootstrap.sh +++ b/bootstrap.sh @@ -181,7 +181,7 @@ function build_tools { make && make install popd - if compare_version "${GCC_VER}" "eq" "2.95.3"; then + if compare_version "${GCC_VER}" "le" "3.4.6"; then mkdir_empty "${BISON}" pushd "${BISON}" "${SOURCES}/${BISON}/configure" \ @@ -545,11 +545,12 @@ function build { install_libamiga build_libnix build_libm + build_gpp - # TODO: C++ compiler needs more testing. - #build_gpp + # TODO: Ixemul is not suited for cross compilation very well. The build + # process compiles some tools with cross compiler and tries to run them + # locally. - # TODO: Ixemul is not suited for cross compilation very well. #build_ixemul } diff --git a/patches/NDK_3.9/Include/include_h/inline/macros.h b/patches/NDK_3.9/Include/include_h/inline/macros.h index 6e75a23..99198d9 100644 --- a/patches/NDK_3.9/Include/include_h/inline/macros.h +++ b/patches/NDK_3.9/Include/include_h/inline/macros.h @@ -24,53 +24,71 @@ #define LP0(offs, rt, name, bt, bn) \ ({ \ - { \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ register rt _##name##_re __asm("d0"); \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register void *const _##name##_bn __asm("a6") = (bn); \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : "=r" (_##name##_re) \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ _##name##_re; \ - } \ + }); \ + _##name##_re2; \ }) #define LP0NR(offs, name, bt, bn) \ ({ \ { \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : /* no output */ \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ } \ }) #define LP1(offs, rt, name, t1, v1, r1, bt, bn) \ ({ \ t1 _##name##_v1 = (v1); \ - { \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ register rt _##name##_re __asm("d0"); \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : "=r" (_##name##_re) \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ _##name##_re; \ - } \ + }); \ + _##name##_re2; \ }) #define LP1NR(offs, name, t1, v1, r1, bt, bn) \ ({ \ t1 _##name##_v1 = (v1); \ { \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : /* no output */ \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ } \ }) @@ -78,16 +96,21 @@ #define LP1A5(offs, rt, name, t1, v1, r1, bt, bn) \ ({ \ t1 _##name##_v1 = (v1); \ - { \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ register rt _##name##_re __asm("d0"); \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ __asm volatile ("exg d7,a5\n\tjsr a6@(-"#offs":W)\n\texg d7,a5" \ - : "=r" (_##name##_re) \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ _##name##_re; \ - } \ + }); \ + _##name##_re2; \ }) /* Only graphics.library/LockLayerRom() and graphics.library/UnlockLayerRom() */ @@ -95,12 +118,16 @@ ({ \ t1 _##name##_v1 = (v1); \ { \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ __asm volatile ("exg d7,a5\n\tjsr a6@(-"#offs":W)\n\texg d7,a5" \ - : /* no output */ \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ } \ }) @@ -109,33 +136,43 @@ ({ \ typedef fpt; \ t1 _##name##_v1 = (v1); \ - { \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ register rt _##name##_re __asm("d0"); \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ __asm volatile ("exg d7,a5\n\tjsr a6@(-"#offs":W)\n\texg d7,a5" \ - : "=r" (_##name##_re) \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ _##name##_re; \ - } \ + }); \ + _##name##_re2; \ }) #define LP2(offs, rt, name, t1, v1, r1, t2, v2, r2, bt, bn) \ ({ \ t1 _##name##_v1 = (v1); \ t2 _##name##_v2 = (v2); \ - { \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ register rt _##name##_re __asm("d0"); \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : "=r" (_##name##_re) \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ _##name##_re; \ - } \ + }); \ + _##name##_re2; \ }) #define LP2NR(offs, name, t1, v1, r1, t2, v2, r2, bt, bn) \ @@ -143,13 +180,17 @@ t1 _##name##_v1 = (v1); \ t2 _##name##_v2 = (v2); \ { \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : /* no output */ \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ } \ }) @@ -158,16 +199,21 @@ ({ \ t1 _##name##_v1 = (v1); \ t2 _##name##_v2 = (v2); \ - { \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ register rt _##name##_re __asm("d0"); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : "=r" (_##name##_re) \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r"(_n1), "rf"(_n2) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ _##name##_re; \ - } \ + }); \ + _##name##_re2; \ }) /* Only dos.library/InternalUnLoadSeg() */ @@ -176,17 +222,22 @@ typedef fpt; \ t1 _##name##_v1 = (v1); \ t2 _##name##_v2 = (v2); \ - { \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ register rt _##name##_re __asm("d0"); \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : "=r" (_##name##_re) \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ _##name##_re; \ - } \ + }); \ + _##name##_re2; \ }) #define LP3(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn) \ @@ -194,18 +245,23 @@ t1 _##name##_v1 = (v1); \ t2 _##name##_v2 = (v2); \ t3 _##name##_v3 = (v3); \ - { \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ register rt _##name##_re __asm("d0"); \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : "=r" (_##name##_re) \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ _##name##_re; \ - } \ + }); \ + _##name##_re2; \ }) #define LP3NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn) \ @@ -214,14 +270,18 @@ t2 _##name##_v2 = (v2); \ t3 _##name##_v3 = (v3); \ { \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : /* no output */ \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ } \ }) @@ -231,17 +291,22 @@ t1 _##name##_v1 = (v1); \ t2 _##name##_v2 = (v2); \ t3 _##name##_v3 = (v3); \ - { \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ register rt _##name##_re __asm("d0"); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : "=r" (_##name##_re) \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r"(_n1), "rf"(_n2), "rf"(_n3) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ _##name##_re; \ - } \ + }); \ + _##name##_re2; \ }) /* Only cia.resource/RemICRVector() */ @@ -251,13 +316,17 @@ t2 _##name##_v2 = (v2); \ t3 _##name##_v3 = (v3); \ { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : /* no output */ \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r"(_n1), "rf"(_n2), "rf"(_n3) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ } \ }) @@ -268,18 +337,23 @@ t1 _##name##_v1 = (v1); \ t2 _##name##_v2 = (v2); \ t3 _##name##_v3 = (v3); \ - { \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ register rt _##name##_re __asm("d0"); \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : "=r" (_##name##_re) \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ _##name##_re; \ - } \ + }); \ + _##name##_re2; \ }) /* Only graphics.library/SetCollision() */ @@ -290,14 +364,18 @@ t2 _##name##_v2 = (v2); \ t3 _##name##_v3 = (v3); \ { \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : /* no output */ \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ } \ }) @@ -307,19 +385,24 @@ t2 _##name##_v2 = (v2); \ t3 _##name##_v3 = (v3); \ t4 _##name##_v4 = (v4); \ - { \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ register rt _##name##_re __asm("d0"); \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ register t4 _n4 __asm(#r4) = _##name##_v4; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : "=r" (_##name##_re) \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ _##name##_re; \ - } \ + }); \ + _##name##_re2; \ }) #define LP4NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn) \ @@ -329,15 +412,19 @@ t3 _##name##_v3 = (v3); \ t4 _##name##_v4 = (v4); \ { \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ register t4 _n4 __asm(#r4) = _##name##_v4; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : /* no output */ \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ } \ }) @@ -349,19 +436,24 @@ t2 _##name##_v2 = (v2); \ t3 _##name##_v3 = (v3); \ t4 _##name##_v4 = (v4); \ - { \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ register rt _##name##_re __asm("d0"); \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ register t4 _n4 __asm(#r4) = _##name##_v4; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : "=r" (_##name##_re) \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ _##name##_re; \ - } \ + }); \ + _##name##_re2; \ }) #define LP5(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \ @@ -371,20 +463,25 @@ t3 _##name##_v3 = (v3); \ t4 _##name##_v4 = (v4); \ t5 _##name##_v5 = (v5); \ - { \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ register rt _##name##_re __asm("d0"); \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ register t4 _n4 __asm(#r4) = _##name##_v4; \ register t5 _n5 __asm(#r5) = _##name##_v5; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : "=r" (_##name##_re) \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ _##name##_re; \ - } \ + }); \ + _##name##_re2; \ }) #define LP5NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \ @@ -395,16 +492,20 @@ t4 _##name##_v4 = (v4); \ t5 _##name##_v5 = (v5); \ { \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ register t4 _n4 __asm(#r4) = _##name##_v4; \ register t5 _n5 __asm(#r5) = _##name##_v5; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : /* no output */ \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ } \ }) @@ -417,20 +518,54 @@ t3 _##name##_v3 = (v3); \ t4 _##name##_v4 = (v4); \ t5 _##name##_v5 = (v5); \ - { \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ register rt _##name##_re __asm("d0"); \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ register t4 _n4 __asm(#r4) = _##name##_v4; \ register t5 _n5 __asm(#r5) = _##name##_v5; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : "=r" (_##name##_re) \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ _##name##_re; \ - } \ + }); \ + _##name##_re2; \ +}) + +/* Only reqtools.library/XXX() */ +#define LP5A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ }) #define LP6(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \ @@ -441,9 +576,13 @@ t4 _##name##_v4 = (v4); \ t5 _##name##_v5 = (v5); \ t6 _##name##_v6 = (v6); \ - { \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ register rt _##name##_re __asm("d0"); \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ @@ -451,11 +590,12 @@ register t5 _n5 __asm(#r5) = _##name##_v5; \ register t6 _n6 __asm(#r6) = _##name##_v6; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : "=r" (_##name##_re) \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ _##name##_re; \ - } \ + }); \ + _##name##_re2; \ }) #define LP6NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \ @@ -467,7 +607,11 @@ t5 _##name##_v5 = (v5); \ t6 _##name##_v6 = (v6); \ { \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ @@ -475,9 +619,9 @@ register t5 _n5 __asm(#r5) = _##name##_v5; \ register t6 _n6 __asm(#r6) = _##name##_v6; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : /* no output */ \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ } \ }) @@ -490,9 +634,13 @@ t5 _##name##_v5 = (v5); \ t6 _##name##_v6 = (v6); \ t7 _##name##_v7 = (v7); \ - { \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ register rt _##name##_re __asm("d0"); \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ @@ -501,11 +649,12 @@ register t6 _n6 __asm(#r6) = _##name##_v6; \ register t7 _n7 __asm(#r7) = _##name##_v7; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : "=r" (_##name##_re) \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ _##name##_re; \ - } \ + }); \ + _##name##_re2; \ }) #define LP7NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \ @@ -518,7 +667,11 @@ t6 _##name##_v6 = (v6); \ t7 _##name##_v7 = (v7); \ { \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ @@ -527,9 +680,9 @@ register t6 _n6 __asm(#r6) = _##name##_v6; \ register t7 _n7 __asm(#r7) = _##name##_v7; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : /* no output */ \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ } \ }) @@ -543,9 +696,13 @@ t5 _##name##_v5 = (v5); \ t6 _##name##_v6 = (v6); \ t7 _##name##_v7 = (v7); \ - { \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ register rt _##name##_re __asm("d0"); \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ @@ -554,11 +711,12 @@ register t6 _n6 __asm(#r6) = _##name##_v6; \ register t7 _n7 __asm(#r7) = _##name##_v7; \ __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ - : "=r" (_##name##_re) \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ _##name##_re; \ - } \ + }); \ + _##name##_re2; \ }) /* Would you believe that there really are beasts that need more than 7 @@ -575,9 +733,13 @@ t6 _##name##_v6 = (v6); \ t7 _##name##_v7 = (v7); \ t8 _##name##_v8 = (v8); \ - { \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ register rt _##name##_re __asm("d0"); \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ @@ -587,11 +749,12 @@ register t7 _n7 __asm(#r7) = _##name##_v7; \ register t8 _n8 __asm(#r8) = _##name##_v8; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : "=r" (_##name##_re) \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ _##name##_re; \ - } \ + }); \ + _##name##_re2; \ }) /* For example intuition.library/ModifyProp() */ @@ -606,7 +769,11 @@ t7 _##name##_v7 = (v7); \ t8 _##name##_v8 = (v8); \ { \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ @@ -616,9 +783,9 @@ register t7 _n7 __asm(#r7) = _##name##_v7; \ register t8 _n8 __asm(#r8) = _##name##_v8; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : /* no output */ \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ } \ }) @@ -634,9 +801,13 @@ t7 _##name##_v7 = (v7); \ t8 _##name##_v8 = (v8); \ t9 _##name##_v9 = (v9); \ - { \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ register rt _##name##_re __asm("d0"); \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ @@ -647,11 +818,12 @@ register t8 _n8 __asm(#r8) = _##name##_v8; \ register t9 _n9 __asm(#r9) = _##name##_v9; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : "=r" (_##name##_re) \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ _##name##_re; \ - } \ + }); \ + _##name##_re2; \ }) /* For example intuition.library/NewModifyProp() */ @@ -667,7 +839,11 @@ t8 _##name##_v8 = (v8); \ t9 _##name##_v9 = (v9); \ { \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ @@ -678,9 +854,9 @@ register t8 _n8 __asm(#r8) = _##name##_v8; \ register t9 _n9 __asm(#r9) = _##name##_v9; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : /* no output */ \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ } \ }) @@ -697,9 +873,13 @@ t8 _##name##_v8 = (v8); \ t9 _##name##_v9 = (v9); \ t10 _##name##_v10 = (v10); \ - { \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ register rt _##name##_re __asm("d0"); \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ @@ -711,11 +891,12 @@ register t9 _n9 __asm(#r9) = _##name##_v9; \ register t10 _n10 __asm(#r10) = _##name##_v10; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : "=r" (_##name##_re) \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ _##name##_re; \ - } \ + }); \ + _##name##_re2; \ }) /* Only graphics.library/BltMaskBitMapRastPort() */ @@ -732,7 +913,11 @@ t9 _##name##_v9 = (v9); \ t10 _##name##_v10 = (v10); \ { \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ @@ -744,9 +929,9 @@ register t9 _n9 __asm(#r9) = _##name##_v9; \ register t10 _n10 __asm(#r10) = _##name##_v10; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : /* no output */ \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ } \ }) @@ -764,9 +949,13 @@ t9 _##name##_v9 = (v9); \ t10 _##name##_v10 = (v10); \ t11 _##name##_v11 = (v11); \ - { \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ register rt _##name##_re __asm("d0"); \ - register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \ + register void *const _##name##_bn __asm("a6") = (bn); \ register t1 _n1 __asm(#r1) = _##name##_v1; \ register t2 _n2 __asm(#r2) = _##name##_v2; \ register t3 _n3 __asm(#r3) = _##name##_v3; \ @@ -779,11 +968,12 @@ register t10 _n10 __asm(#r10) = _##name##_v10; \ register t11 _n11 __asm(#r11) = _##name##_v11; \ __asm volatile ("jsr a6@(-"#offs":W)" \ - : "=r" (_##name##_re) \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10), "rf"(_n11) \ - : "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \ + : "fp0", "fp1", "cc", "memory"); \ _##name##_re; \ - } \ + }); \ + _##name##_re2; \ }) #endif /* __INLINE_MACROS_H */