Update README.md

2026-09-12 04:02:46 +00:00 · 2016-03-10 10:46:17 +11:00
parent 1e8077a1a4
commit d0868b7cb7
1 changed files with 2 additions and 1 deletions
@@ -40,7 +40,8 @@ Then, during the vertical blank, depending on the LOF bit in the VPOSR register,
 ```

 This example allows your to enable/disable INTERLACE mode in the [Makefile](Makefile):
-     ```
+
+	```
 INTERLACE=1
 ```