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193 lines
7.2 KiB
C
193 lines
7.2 KiB
C
/*
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1982, 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Utah $Hdr: cpu.h 1.16 91/03/25$
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*
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* @(#)cpu.h 7.7 (Berkeley) 6/27/91
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*/
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/*
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* Exported definitions unique to hp300/68k cpu support.
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*/
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/*
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* definitions of cpu-dependent requirements
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* referenced in generic code
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*/
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#define COPY_SIGCODE /* copy sigcode above user stack in exec */
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/*
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* function vs. inline configuration;
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* these are defined to get generic functions
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* rather than inline or machine-dependent implementations
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*/
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#define NEED_MINMAX /* need {,i,l,ul}{min,max} functions */
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#undef NEED_FFS /* don't need ffs function */
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#undef NEED_BCMP /* don't need bcmp function */
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#undef NEED_STRLEN /* don't need strlen function */
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#define cpu_exec(p) /* nothing */
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#define cpu_wait(p) /* nothing */
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/*
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* Arguments to hardclock, softclock and gatherstats
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* encapsulate the previous machine state in an opaque
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* clockframe; for amiga, use just what Exec
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* leaves on the stack (not documented, thus private !!!)
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*/
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typedef struct intrframe {
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int __ALIGN2__ exec_regs[6];
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u_short ps;
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int __ALIGN2__ pc;
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} __PACKED__ clockframe;
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#define CLKF_USERMODE(framep) (((framep)->ps & PSL_S) == 0)
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#define CLKF_BASEPRI(framep) (((framep)->ps & PSL_IPL7) == 0)
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#define CLKF_PC(framep) ((framep)->pc)
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#ifdef _KERNEL
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/*
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* Preempt the current process if in interrupt from user mode,
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* or after the current trap/syscall if in system mode.
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*/
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/* #define need_resched() { want_resched++; aston(); } */
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/* don't do anything on the Amiga, we don't use the BSD scheduler */
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#define need_resched()
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/*
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* Give a profiling tick to the current process from the softclock
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* interrupt. On hp300, request an ast to send us through trap(),
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* marking the proc as needing a profiling tick.
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*/
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/* #define profile_tick(p, framep) { (p)->p_flag |= SOWEUPC; aston(); } */
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static void inline
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profile_tick (struct proc *p, clockframe *framep)
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{
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if (p->p_stats->p_prof.pr_scale)
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addupc (CLKF_PC(framep), &p->p_stats->p_prof, 1);
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}
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/*
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* Notify the current process (p) that it has a signal pending,
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* process as soon as possible.
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*
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* NOTE: this function assumes it is only called with p==curproc!!!
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*/
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static void inline
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signotify (struct proc *p)
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{
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u_int sr, curr_disp;
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/* NOTE: the context switch is done to make sure sig_launch() is called as
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* soon as possible in the respective task. It's not nice if you can
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* return from a kill() to yourself, before the signal handler had a
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* chance to react accordingly to the signal..
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*/
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asm volatile ("
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movel a5,a0
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FIXME: It is uncertain if the below line needs to have the +2 removed or not.
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FIXME: It is also uncertain if this file is even used. If so, this will error out.
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lea Lget_sr-.+2,a5 | Never used
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movel 4:w,a6
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jsr a6@(-0x1e)
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movel a1,%0
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bra Lskip
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Lget_sr:
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movew sp@,a1 | get sr register from the calling function
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rte
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Lskip:
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movel a0,a5
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" : "=g" (sr) : : "a0", "a1", "a6");
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if (sr & PSL_S) return; /* if in Supervisor, don't do this... */
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/* this quite brute-force method, but the only thing I could think of that
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* really guarantees that there was a context switch..
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* DispCount is the dispatch counter of Exec, thus we wait until there was
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* at least one such dispatch ;-)
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*/
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for (curr_disp = SysBase->DispCount; curr_disp == SysBase->DispCount; ) ;
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}
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/* what is this supposed to do? i.e. how is it different than startrtclock? */
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#define enablertclock()
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#endif /* _KERNEL */
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/*
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* 68851 and 68030 MMU
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*/
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#define PMMU_LVLMASK 0x0007
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#define PMMU_INV 0x0400
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#define PMMU_WP 0x0800
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#define PMMU_ALV 0x1000
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#define PMMU_SO 0x2000
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#define PMMU_LV 0x4000
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#define PMMU_BE 0x8000
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#define PMMU_FAULT (PMMU_WP|PMMU_INV)
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/* 680X0 function codes */
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#define FC_USERD 1 /* user data space */
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#define FC_USERP 2 /* user program space */
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#define FC_PURGE 3 /* HPMMU: clear TLB entries */
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#define FC_SUPERD 5 /* supervisor data space */
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#define FC_SUPERP 6 /* supervisor program space */
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#define FC_CPU 7 /* CPU space */
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/* fields in the 68020 cache control register */
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#define IC_ENABLE 0x0001 /* enable instruction cache */
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#define IC_FREEZE 0x0002 /* freeze instruction cache */
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#define IC_CE 0x0004 /* clear instruction cache entry */
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#define IC_CLR 0x0008 /* clear entire instruction cache */
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/* additional fields in the 68030 cache control register */
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#define IC_BE 0x0010 /* instruction burst enable */
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#define DC_ENABLE 0x0100 /* data cache enable */
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#define DC_FREEZE 0x0200 /* data cache freeze */
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#define DC_CE 0x0400 /* clear data cache entry */
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#define DC_CLR 0x0800 /* clear entire data cache */
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#define DC_BE 0x1000 /* data burst enable */
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#define DC_WA 0x2000 /* write allocate */
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#define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
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#define CACHE_OFF (DC_CLR|IC_CLR)
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#define CACHE_CLR (CACHE_ON)
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#define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
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#define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
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