Update README.md

2026-09-12 21:52:00 +00:00 · 2016-03-10 10:46:39 +11:00
parent d0868b7cb7
commit 1e4986a159
1 changed files with 1 additions and 1 deletions
@@ -41,7 +41,7 @@ Then, during the vertical blank, depending on the LOF bit in the VPOSR register,

 This example allows your to enable/disable INTERLACE mode in the [Makefile](Makefile):

-	```
+    ```
 INTERLACE=1
 ```